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Registro Completo |
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Biblioteca(s): |
Embrapa Agricultura Digital. |
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Data corrente: |
15/12/1997 |
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Data da última atualização: |
16/03/2011 |
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Autoria: |
MUCHERONI, M. L.; CAMPOS, G. L. de; PEREIRA, R. da S. |
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Afiliação: |
MARCOS LUIZ MUCHERONI, UFSCar; GERALDO LINIO DE CAMPOS, USP; RENATO DA SILVA PEREIRA, UFSCar. |
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Título: |
A simple hardware description language with timing constraints. |
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Ano de publicação: |
1997 |
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Fonte/Imprenta: |
In: CONGRESO INTERNACIONAL DE INGENIERIA INFORMÁTICA, 3., 1997, Buenos Aires. Proceedings... Buenos Aires: Universidad de Buenos Aires, Facultad de Inginieria, 1997. |
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Páginas: |
p. 328-335. |
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Idioma: |
Inglês |
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Conteúdo: |
Many tools and environments have been developed to aid hardware designers to carry out the implementation of Application-Specific Integrated Circuits (ASICs). Most of them are aimed at implementing the lower level details of a hardware target, such as layout (placement, routing, area sizing, partitioning and others). It has also been developed to reduce design effort at low level implementation considering any project constraints: area, timing, power consumption and soon. At a higher level, these tools have been written in High Level Languages (HLLs) using different objectives: algorithms, hardware, communication, specification and environments. An important decision during implementation is what level and which will be used to make the system. Tools of software and hardware synthesis are desired, in many levels: flowcharts, algorithms, RTL descriptions, Boolean expressions, transistor and timing diagrams. Different tools have different power of expression, but also different levels of difficulty of implementation in time and effort. The Hardware Description Language (HDL) is basically a tradeoff between the "degree of expression" and the "difficulty of implementation". The question that arises is what features are essential in a simple and fast system design. Thus, the HDL should reduce drastically the effort required by the designer to express a particular feature of the design (e.g., area or timing) without sacrificing the project itself. The timing constraints is one of the most important features and its implementation in many description styles and application domains is one of the goals of this present work. High-level simulations are often referred to as behavioral, because only overall behavior of component devices is made externally visible. On the other hand, structural simulation represents a precise description of components. The HDL can have a certain level of detail where any feature is monitored. A general rule, the higher the level of detail the larger is the computing time consumed. This time can be significant if the simulation is structural where it may have from 10 or 100 million of gates and this time grows in logarithm scale. Some of these languages are HardwareC, VHDL, Statecharts, Silage, SpecCharts and Verilog. A special HDL is proposed using timing constraints and unambiguous specification. This simple and specific HDL supporting net-list of components has: 1) structural hierarchy is necessary for timing specifications. Due to the complexity in terms of specification, few unambiguous statements will result in fast implementation; 2) scheduling is essential, since a target system consists of several concurrent parts of hardware whose actions may take place simultaneously. So, statement-level concurrence is required. 3) Programming constructs, which are required to specify the aspects of design - the computation carried out by an algorithm. Also, some structures are necessary: block, entity, component, connection and signals. MenosMany tools and environments have been developed to aid hardware designers to carry out the implementation of Application-Specific Integrated Circuits (ASICs). Most of them are aimed at implementing the lower level details of a hardware target, such as layout (placement, routing, area sizing, partitioning and others). It has also been developed to reduce design effort at low level implementation considering any project constraints: area, timing, power consumption and soon. At a higher level, these tools have been written in High Level Languages (HLLs) using different objectives: algorithms, hardware, communication, specification and environments. An important decision during implementation is what level and which will be used to make the system. Tools of software and hardware synthesis are desired, in many levels: flowcharts, algorithms, RTL descriptions, Boolean expressions, transistor and timing diagrams. Different tools have different power of expression, but also different levels of difficulty of implementation in time and effort. The Hardware Description Language (HDL) is basically a tradeoff between the "degree of expression" and the "difficulty of implementation". The question that arises is what features are essential in a simple and fast system design. Thus, the HDL should reduce drastically the effort required by the designer to express a particular feature of the design (e.g., area or timing) without sacrificing the project itself. The timing constraints is one of ... Mostrar Tudo |
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Palavras-Chave: |
Linguagem para hardware; Modelagem de hardware; Modeling. |
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Thesagro: |
Informática. |
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Thesaurus Nal: |
Computer hardware. |
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Categoria do assunto: |
X Pesquisa, Tecnologia e Engenharia |
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Marc: |
LEADER 03721naa a2200217 a 4500
001 1005523
005 2011-03-16
008 1997 bl uuuu u00u1 u #d
100 1 $aMUCHERONI, M. L.
245 $aA simple hardware description language with timing constraints.
260 $c1997
300 $ap. 328-335.
520 $aMany tools and environments have been developed to aid hardware designers to carry out the implementation of Application-Specific Integrated Circuits (ASICs). Most of them are aimed at implementing the lower level details of a hardware target, such as layout (placement, routing, area sizing, partitioning and others). It has also been developed to reduce design effort at low level implementation considering any project constraints: area, timing, power consumption and soon. At a higher level, these tools have been written in High Level Languages (HLLs) using different objectives: algorithms, hardware, communication, specification and environments. An important decision during implementation is what level and which will be used to make the system. Tools of software and hardware synthesis are desired, in many levels: flowcharts, algorithms, RTL descriptions, Boolean expressions, transistor and timing diagrams. Different tools have different power of expression, but also different levels of difficulty of implementation in time and effort. The Hardware Description Language (HDL) is basically a tradeoff between the "degree of expression" and the "difficulty of implementation". The question that arises is what features are essential in a simple and fast system design. Thus, the HDL should reduce drastically the effort required by the designer to express a particular feature of the design (e.g., area or timing) without sacrificing the project itself. The timing constraints is one of the most important features and its implementation in many description styles and application domains is one of the goals of this present work. High-level simulations are often referred to as behavioral, because only overall behavior of component devices is made externally visible. On the other hand, structural simulation represents a precise description of components. The HDL can have a certain level of detail where any feature is monitored. A general rule, the higher the level of detail the larger is the computing time consumed. This time can be significant if the simulation is structural where it may have from 10 or 100 million of gates and this time grows in logarithm scale. Some of these languages are HardwareC, VHDL, Statecharts, Silage, SpecCharts and Verilog. A special HDL is proposed using timing constraints and unambiguous specification. This simple and specific HDL supporting net-list of components has: 1) structural hierarchy is necessary for timing specifications. Due to the complexity in terms of specification, few unambiguous statements will result in fast implementation; 2) scheduling is essential, since a target system consists of several concurrent parts of hardware whose actions may take place simultaneously. So, statement-level concurrence is required. 3) Programming constructs, which are required to specify the aspects of design - the computation carried out by an algorithm. Also, some structures are necessary: block, entity, component, connection and signals.
650 $aComputer hardware
650 $aInformática
653 $aLinguagem para hardware
653 $aModelagem de hardware
653 $aModeling
700 1 $aCAMPOS, G. L. de
700 1 $aPEREIRA, R. da S.
773 $tIn: CONGRESO INTERNACIONAL DE INGENIERIA INFORMÁTICA, 3., 1997, Buenos Aires. Proceedings... Buenos Aires: Universidad de Buenos Aires, Facultad de Inginieria, 1997.
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Registro original: |
Embrapa Agricultura Digital (CNPTIA) |
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 | Acesso ao texto completo restrito à biblioteca da Embrapa Florestas. Para informações adicionais entre em contato com cnpf.biblioteca@embrapa.br. |
Registro Completo
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Biblioteca(s): |
Embrapa Florestas. |
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Data corrente: |
09/11/2009 |
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Data da última atualização: |
28/10/2010 |
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Tipo da produção científica: |
Resumo em Anais de Congresso |
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Autoria: |
FRITZSONS, E.; MANTOVANI, L. E.; CARPANEZZI, A. A.; WREGE, M. S.; GARRASTAZU, M. C.; CHAVES NETO, A. |
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Afiliação: |
ELENICE FRITZSONS, CNPF; LUIZ EDUARDO MANTOVANI, UFPR; ANTONIO APARECIDO CARPANEZZI, CNPF; MARCOS SILVEIRA WREGE, CNPF; MARILICE CORDEIRO GARRASTAZU, CNPF; ANSELMO CHAVES NETO, UFPR. |
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Título: |
Ecological regions map for forest plantation at Paraná state, Brazil. |
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Ano de publicação: |
2009 |
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Fonte/Imprenta: |
In: CONGRESO FORESTAL MUNDIAL, 13., 2009, Buenos Aires. Desarrollo forestal: equilibrio vital. Argentina: FAO, 2009. |
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Idioma: |
Inglês |
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Notas: |
Resumo. |
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Palavras-Chave: |
Paraná; Plantação florestal. |
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Categoria do assunto: |
K Ciência Florestal e Produtos de Origem Vegetal |
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Marc: |
LEADER 00641naa a2200205 a 4500
001 1574289
005 2010-10-28
008 2009 bl --- 0-- u #d
100 1 $aFRITZSONS, E.
245 $aEcological regions map for forest plantation at Paraná state, Brazil.
260 $c2009
500 $aResumo.
653 $aParaná
653 $aPlantação florestal
700 1 $aMANTOVANI, L. E.
700 1 $aCARPANEZZI, A. A.
700 1 $aWREGE, M. S.
700 1 $aGARRASTAZU, M. C.
700 1 $aCHAVES NETO, A.
773 $tIn: CONGRESO FORESTAL MUNDIAL, 13., 2009, Buenos Aires. Desarrollo forestal: equilibrio vital. Argentina: FAO, 2009.
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Registro original: |
Embrapa Florestas (CNPF) |
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