Data/hora: 21/06/2024 03:14:17

Biblioteca(s): | Ebooks.
Data corrente: | 07/01/2011
Data da última atualização: | 16/06/2011
Autoria: | FUJITA, M.; GHOSH, I.; PRASAD, M.
Afiliação: | Masahiro Fujita; I. Ghosh; Mukul Prasad.
Título: | Verification techniques for system-level design
Ano de publicação: | 2008
Fonte/Imprenta: | Amsterdam; Boston: Morgan Kaufmann Publishers, c2008.
Páginas: | viii, 240 p. :
Descrição Física: | ill. ;25 cm.
Série: | The Morgan Kaufmann series in systems on silicon
ISBN: | 9780123706164
Idioma: | Inglês
Conteúdo: | This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs. First book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs. Formal verification of high-level designs (RTL or higher). Verification techniques are discussed with associated system-level design methodology.
Palavras-Chave: | Formal methods (Computer science); Integrated circuits; Systems on a chip.
Categoria do assunto: | --
URL: | http://www.sciencedirect.com/science/book/9780123706164
Registro original: | Ebooks (Ebooks)